Method and system for regulating the decision threshold and the sampling clock phase of a data regenerator for a binary signal

ABSTRACT

A method and system for regulating the decision threshold and the sampling clock phase of a data regenerator for a binary signal, wherein error correction signals for erroneous 1-bits and 0-bits are used for regulating the decision threshold of a decision stage, and further phase correction signals between transitions of binary signals serve for the phase regulation of a sampling clock signal.

BACKGROUND OF THE INVENTION

[0001] The present invention relates to a method for regulating thedecision threshold and/or the phase of a sampling clock signal of a dataregenerator for a binary signal by evaluation of error correctionsignals.

[0002] Numerous circuits are known in which the decision threshold of adata regenerator and the phase of the sampling clock signal arecorrected on the basis of criteria which are obtained from the receivedsignal. In addition, there is a further group of data regeneratorswhich, in the case of a redundant binary signal, utilize the errordetection/error correction for controlling the decision threshold andthe phase angle.

[0003] The published patent application DE 197 17 642 A1 discloses amethod in which the decision threshold and the phase are varied with theaid of a control until the error rate reaches a minimum. In this method,the phase angle and the threshold always hunt around the optimum.

[0004] The U.S. Pat. No. 4,360,926 discloses a digital PLL (phase-lockedloop) in which a phase comparison is carried out between the receivedsignal and the sampling clock signal and, in addition, information ofthe error detector is used for optimization.

[0005] It is an object of the present invention, therefore, to develop amethod and system for optimizing the decision threshold and/or the phaseangle of the sampling clock signal.

SUMMARY OF THE INVENTION

[0006] Pursuant to the present invention, either the decision thresholdor the sampling phase, or both, can be regulated by using the correctionsignals in connection with taking account of the logic state of thebinary signal.

[0007] One advantage of this method is that it operates even atrelatively high bit error rates.

[0008] In order to regulate the decision threshold, use is made of thedifference between the number of corrected 1-bits, that is to say thecorrected bit becomes a binary zero, and the number of corrected 0-bits,where correction into a binary one is effected. It is also possible toevaluate the quotient of corrected 1-bits to 0-bits (or vice versa). Inthe case of unbalanced codes, the relation of binary ones to binaryzeros should be taken into account.

[0009] The correction signals are likewise used for regulating the phaseof a sampling clock signal. For this purpose, a check is made todetermine whether the number of corrections is larger before or after atransition between two different (corrected) binary states.

[0010] A corresponding arrangement can be achieved in an all-digitalmanner, thereby avoiding problems due to temperature dependence or agingas in the conventional clock regenerators.

[0011] It is also advantageous to monitor the frequency of correctionswhich, under constant transmission conditions, reproduces the mode ofoperation of the regulation. With optimized sampling, the frequency ofcorrections is a criterion for the signal quality which is additionallyused for controlling the time constants of the regulating devices.

[0012] It is also advantageous to limit the variation range of thedecision threshold in order for the operational capability to always beensured.

[0013] The method according to the present invention also can becombined with the conventional analog methods in which the receivedsignal is compared with the sampling clock signal for the purpose ofphase correction.

[0014] Additional features and advantages of the present invention aredescribed in, and will be apparent from, the following DetailedDescription of the Invention and the Figures.

BRIEF DESCRIPTION OF THE FIGURES

[0015]FIG. 1 shows a basic circuit diagram of a data regenerator.

[0016]FIG. 2 shows a timing diagram for the regulation of the decisionthreshold.

[0017]FIG. 3 shows a timing diagram for the regulation of the phase ofthe sampling clock signal.

DETAILED DESCRIPTION OF THE INVENTION

[0018]FIG. 1 illustrates the data regenerator 1-6 according to thepresent invention. The signal BS is fed to a decision stage 1 andcompared with a comparison value, the decision threshold TH. The binaryoutput signal of the decision stage 1 is fed to the data input D of asampling flip-flop 2 and its data bits are ideally latched (stored), ineach case, in the bit center with a sampling clock signal TS generatedby a controlled oscillator (VCO) (not illustrated) of a clockregenerator 3 (e.g., a phase-locked loop PLL). From the data output ofthe sampling flip-flop 2, the binary signal passes to an errorcorrection device (FEC) 4, which outputs a corrected binary signal CBSat its data output.

[0019] On the basis of redundant information, the error correctiondevice 4 identifies which bits of the binary signal are disturbed andcorrects them by inversion. The correction signals are combined herewith the binary state of the as-yet-uncorrected bit (logic combinationwith the state of the corrected bit is equivalent) and output ascorrection signals K1 and K0, respectively. K1 refers to a bit stored asbinary state “1” in the sampling flip-flop 2 being corrected into thebinary state “0”; K0 refers to a correction of the binary state “0” intothe binary state “1”. A decision threshold regulator 5 forms thedifference between the sums of the K1 correction signals and K0correction signals ΣK1-ΣK0 and correspondingly shifts the threshold THof the decision stage 1. The measurement intervals can be adapted to thebit error rate. It is also possible to count up to a specific number ofcorrection operations, or have both methods combined.

[0020] The diagram of FIG. 2 illustrates the temporal profile of theamplitude A of an undisturbed binary signal BS as a function of time tas a solid line, which signal is sampled at the receiving end atinstants T₀, T₁, T₂ . . . . However, the decision threshold (samplingthreshold) TH is not at its ideal value TH₀ (broken line), butsignificantly lower. An ideal signal BS is now still sampled correctly.However, if signal distortions now occur, then in the case of adisturbed signal (shown by a broken line), a corruption of the binary“0” into a binary “1” is very easily possible, which is reversed againby a correction operation K1. If the correction signals K1 outweigh thefar less likely correction signals K0, then the decision threshold THmust be shifted in the direction of the optimum threshold S₀; in thiscase, toward higher values. Assuming that the binary “1” has the higherlevel, the following holds true for the decision threshold TH:

[0021] (1) ΣK1>ΣK0→TH higher

[0022] (2) ΣK1<ΣK0→TH lower

[0023] In the case of an unbalanced code, the following holds true(including mathematical transformations): $\begin{matrix} {\frac{\sum{K1}}{NO} > \frac{\sum{K0}}{N1}}\Rightarrow{{TH}\quad {higher}}  & (3) \\ {\frac{\sum{K1}}{N0} < \frac{\sum{K0}}{N1}}\Rightarrow{{TH}\quad {lower}}  & (4)\end{matrix}$

[0024] It is equally possible, as mentioned in the introduction, tocompare the quotients of the summed correction signals with the quotientof the sum of the binary zeros N0 with the sum of the binary ones N1,whereby the ratio of binary zeros to ones is likewise taken intoaccount.

[0025] The range in which it is possible to shift the decision thresholdcan be limited, so that the clock regenerator or the receiver alwaysremains functional.

[0026] In a similar manner, correction signals KBT (before transition)and KAT (after transition) are obtained before and after the transitionbetween two binary states. This is again done by combination of thecorrection signal with, in each case, a (corrected) bit before and afterthe transition between two binary states of the corrected signal, whichgenerally corresponds to the original binary signal.

[0027]FIG. 3 again shows the amplitude profile of the binary signal BSas a function of time t. The desired sampling instants are denoted byT₀, T₁, T₂, . . . , whereas the actual instants are denoted by T_(0i),T_(1i), T_(2i). A phase error φ of the sampling signal relative to theideal sampling instant or the signal, referred to as phase for short,increases the likelihood of incorrect samples in the case of statechanges. By virtue of the fact that the sampling instant t_(0i) movesnearer to the transition between the binary states, an “erroneous”sampling is effected in the case of additional influencing/disturbancesof the binary signal BS (shown by a broken line). In this case, a 0-bitis sampled, which is corrected into a 1-bit by a correction operationKBT. By contrast, the phase shift of the clock signal is unimportant atthe instant T_(1i), since no signal transition takes place in thevicinity. Only in the vicinity of the instant T_(2i) does the binarystate change again from “0” to “1”, as a result of which the likelihoodof erroneous sampling increases again. In the case of the bit sequenceillustrated, it is highly likely that there will be more phasecorrections KBT during the transition from “1” to “0”, as a result ofthe binary state “0” that is then maintained, than after the transition.

[0028] If the bit is incorrectly sampled as “0” before the signaltransition in the case of a disturbed signal (shown by a broken line)and subsequently corrected, a phase correction signal KBT is output;which, in this case, indicates the correction of a binary “0” into a“1”. Since the next (if appropriately corrected) bit is a zero, atransition between the binary states is present in the ideal oralternatively corrected binary signal. By contrast, if the bit iscorrected after the transition, a phase correction signal KAT (AfterTransition) is output. These signals are summed in a phase regulator 6and the sums are compared with one another. The result of thiscomparison, a clock phase correction signal PH, controls or corrects thephase angle of the clock signal TS in relation to the binary signal BSuntil the number of both correction signals has the same value. Thefollowing holds true:

[0029] (5) ΣKBT>ΣKAT→phase TS accelerate or increase frequency

[0030] (6) ΣKBT<ΣKAT→phase TS decelerate or lower frequency

[0031] The phase difference φ of the clock signal TS relative to theideal sampling instants T₀, T₁, T₂, . . . for the binary signal BS is tobe reduced in the example illustrated. The same applies,correspondingly, in the case of a leading phase of the clock signal.

[0032] In the exemplary embodiment of FIG. 1, the phase of the clocksignal generated by the clock regenerator 3, designed here as aphase-locked loop (PLL), is corrected. As a rule, the correction will besmall and can be limited. The phase can be changed in any desiredmanner; particularly, by simple intervention in the phase-locked loop asin the exemplary embodiment.

[0033] Without additional measures, the method of the present inventionoperates only if, before or after a transition between the binarystates, the binary state is preserved for at least one further bit. Inthe case of a 1010 change, it is highly likely that the phase correctionsignals will cancel out. They also can be suppressed by evaluation ofthe bit sequences. In the case of a continual change of binary zeros andbinary ones, the phase correction is not achieved without additionalmeasures. However, this situation does not occur in customary datatransmission and, moreover, the function of the analog phase regulationis preserved.

[0034] By monitoring the correction rate, it is possible to check thetransmission link and control the regulating devices of the dataregenerator.

[0035] Although the present invention has been described with referenceto specific embodiments, those of skill in the art will recognize thatchanges may be made thereto without departing from the spirit and scopeof the invention as set forth in the hereafter appended claims.

1. A method for regulating a decision threshold in a sampling of abinary signal by evaluation of error correction signals, the methodcomprising the steps of: counting both a number of 1-bits detected aserroneous and a number of 0-bits detected as erroneous; evaluating thenumber of 1-bits detected as erroneous and the number of 0-bits detectedas erroneous; and adjusting the decision threshold correspondingly toachieve an optimum ratio of the number of 1-bits detected as erroneousand the number of 0-bits detected as erroneous.
 2. A method forregulating a decision threshold in a sampling of a binary signal asclaimed in claim 1, the method further comprising the steps of: forminga difference between the number of 1-bits detected as erroneous and thenumber of 0-bits detected as erroneous; and converting the differenceinto an actuating signal for the decision threshold.
 3. A method forregulating a decision threshold in a sampling of a binary signal asclaimed in claim 2, the method further comprising the step of settingthe decision threshold, for balanced codes, such that the differencebecomes zero.
 4. A method for regulating a decision threshold in asampling of a binary signal as claimed in claim 2, the method furthercomprising the step of taking into account, for unbalanced codes, aratio of a total number of 1-bits to a total number of 0-bits of thebinary signal.
 5. A method for regulating a decision threshold in asampling of a binary signal as claimed in claim 4, the method furthercomprising the steps of: forming a first ratio of the number of 1-bitsdetected as erroneous to the total number of 0-bits; forming a secondratio of the number of 0-bits detected as erroneous to the total numberof 1-bits; comparing the first and second ratios; and setting thedecision threshold based on the comparison such that a differencebetween the first and second ratios becomes zero.
 6. A method forregulating a relative phase of a sampling clock signal with respect to aphase of a binary signal by evaluation of error correction signals, themethod comprising the steps of: counting and evaluating a number of bitsdetected as erroneous before a transition between binary states and anumber of bits detected as erroneous after a transition between thebinary states; and adjusting the phase of the sampling clock signal suchthat at least approximately the same number of bits detected aserroneous occurs before and after the transition between the binarystates.
 7. A method for regulating a relative phase of a sampling clocksignal with respect to a phase of a binary signal as claimed in claim 6,wherein evaluation only occurs for at least one of transitions forspecific binary sequences and a specific transition between the binarystates.
 8. A method for regulating a relative phase of a sampling clocksignal with respect to a phase of a binary signal as claimed in claim 6,wherein the error correction signals of an error correction device areat least one of evaluated in a manner logically combined with therespective binary state of a bit detected as erroneous and evaluatedbefore and after the transition between the binary states as phasecorrection signals.
 9. A method for regulating a relative phase of asampling clock signal with respect to a phase of a binary signal asclaimed in claim 6, wherein a decision threshold for the binary signaland the phase of the sampling clock signal are regulated.
 10. A methodfor regulating a relative phase of a sampling clock signal with respectto a phase of a binary signal as claimed in claim 6, wherein aproportion of bits detected as erroneous is used for controlling a timeconstant of a regulating system.
 11. A system for regulating a decisionthreshold of a data regenerator having a decision stage, to which abinary signal and a comparison signal are fed, the system comprising: asampling flip-flop having a data input connected to an output of thedecision stage; a controllable clock regenerator which generates asampling clock signal for the sampling flip-flop; an error correctiondevice for controlling the controllable clock regenerator; and aregulator, a first correction signal being fed to the regulator from theerror correction device which indicates a correction of a 1-bit, and asecond correction signal being fed to the regulator from the errorcorrection device which indicates a correction of a 0-bit, wherein theregulator separately sums and assesses the first and second correctionsignals and generates a control signal which determines a magnitude ofthe comparison signal.
 12. A system for regulating a decision thresholdof a data regenerator as claimed in claim 11, wherein a phase of thesampling clock signal is also regulated.
 13. A system for regulating aphase of a sampling clock signal, the system comprising: a clockregenerator for generating the sampling clock signal; an errorcorrection device for controlling the clock regenerator; a samplingflip-flop into which a binary signal is latched via the sampling clocksignal; and a regulator, a first phase correction signal being fed tothe regulator from the error correction device which indicates acorrection of a bit before a signal transition between two binarystates, and a second phase correction signal being fed to the regulatorwhich indicates a correction of a bit after a signal transition betweentwo binary states, the regulator counting the correction signals andcomparing the sums to generate a phase correction signal which generatesthe phase of the sampling clock signal such that at least approximatelya same number of correction signals occurs before and after a transitionbetween the binary state.
 14. A system for regulating a phase of asampling clock signal as claimed in claim 13, wherein a decisionthreshold of the sampling clock signal is also regulated.